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TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI Expand file tree Collapse file tree 5 files changed +23
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lines changed Original file line number Diff line number Diff line change @@ -51,14 +51,14 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE {
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RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
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}
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- RW_IRAM1 (MBED_RAM_START ) { ; RW data
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+ RW_IRAM1 (MBED_RAM1_START ) { ; RW data
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.ANY (+RW +ZI)
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}
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- ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
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+ ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM1_START + MBED_RAM1_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
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}
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- ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE ) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
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+ ARM_LIB_STACK (MBED_RAM1_START + MBED_RAM1_SIZE ) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
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}
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RW_DMARxDscrTab 0x30040000 0x60 {
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{
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FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
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DTCMRAM (rwx) : ORIGIN = NVIC_RAM_VECTOR_ADDRESS + VECTORS_SIZE, LENGTH = 128K - VECTORS_SIZE
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- RAM (xrw) : ORIGIN = MBED_RAM_START , LENGTH = MBED_RAM_SIZE
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+ RAM (xrw) : ORIGIN = MBED_RAM1_START , LENGTH = MBED_RAM1_SIZE
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RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K
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RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K
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ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
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#endif
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#if !defined(MBED_ROM_SIZE )
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+ // 0x0x08000000-0x080FFFFF Bank1 (8 x 128K sectors)
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+ // 0x0x08100000-0x081FFFFF Bank2 (8 x 128K sectors)
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#define MBED_ROM_SIZE 0x200000 // 2.0 MB
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#endif
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#if !defined(MBED_RAM_START )
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- #define MBED_RAM_START 0x24000000
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+ #define MBED_RAM_START 0x20000000
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#endif
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#if !defined(MBED_RAM_SIZE )
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- #define MBED_RAM_SIZE 0x80000 // 512 KB
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+ // 0x38000000 - 0x3800FFFF 64K SRAM4
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+ // 0x30040000 - 0x30047FFF 32K SRAM3
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+ // 0x30020000 - 0x3003FFFF 128K SRAM2
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+ // 0x30000000 - 0x3001FFFF 128K SRAM1
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+ // 0x24000000 - 0x2407FFFF 512K AXI SRAM
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+ // 0x20000000 - 0x2001FFFF 128K DTCM
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+ #define MBED_RAM_SIZE 0x20000 // 128 KB
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#endif
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- // DON'T USE MBED_RAM1_START and MBED_RAM1_SIZE (wrong values in tools/arm_pack_manager/index.json)
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+ #if !defined(MBED_RAM1_START )
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+ #define MBED_RAM1_START 0x24000000
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+ #endif
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+
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+ #if !defined(MBED_RAM1_SIZE )
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+ #define MBED_RAM1_SIZE 0x80000 // 512 KB
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+ #endif
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#define NVIC_NUM_VECTORS 166
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- #define NVIC_RAM_VECTOR_ADDRESS 0x20000000
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+ #define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START
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#endif
Original file line number Diff line number Diff line change 3197
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],
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"public" : false ,
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"core" : " Cortex-M7FD" ,
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- "mbed_rom_start" : " 0x08000000" ,
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- "mbed_rom_size" : " 0x200000" ,
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- "mbed_ram_start" : " 0x24000000" ,
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- "mbed_ram_size" : " 0x80000" ,
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"extra_labels_add" : [
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" STM32H743xI"
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],
Original file line number Diff line number Diff line change @@ -437822,46 +437822,6 @@
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"ram_start": 536870912,
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"size": 2097152,
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"start": 134217728
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- },
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- {
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- "default": false,
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- "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G.FLM",
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- "ram_size": 65524,
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- "ram_start": 536870912,
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- "size": 67108864,
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- "start": 2415919104
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- },
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- {
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- "default": false,
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- "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM",
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- "ram_size": 65524,
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- "ram_start": 536870912,
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- "size": 134217728,
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- "start": 2415919104
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- },
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- {
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- "default": false,
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- "file_name": "CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM",
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- "ram_size": 65524,
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- "ram_start": 536870912,
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- "size": 134217728,
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- "start": 2415919104
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- },
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- {
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- "default": false,
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- "file_name": "CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM",
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- "ram_size": 65524,
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- "ram_start": 536870912,
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- "size": 134217728,
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- "start": 2415919104
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- },
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- {
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- "default": false,
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- "file_name": "CMSIS/Flash/STM32H743I-eval_FMC.FLM",
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- "ram_size": 65524,
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- "ram_start": 536870912,
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- "size": 16777216,
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- "start": 1610612736
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}
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],
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"family": "STM32H7 Series",
@@ -437913,25 +437873,10 @@
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"write": false
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},
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"default": true,
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- "size": 1048576,
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+ "size": 2097152,
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"start": 134217728,
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"startup": true
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},
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- "IROM2": {
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- "access": {
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- "execute": true,
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- "non_secure": false,
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- "non_secure_callable": false,
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- "peripheral": false,
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- "read": true,
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- "secure": false,
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- "write": false
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- },
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- "default": true,
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- "size": 1048576,
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- "start": 135266304,
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- "startup": true
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- },
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"RAM_D2": {
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"access": {
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"execute": true,
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