From 0ce9d198b2127878668c6581fa66e4a7fb954439 Mon Sep 17 00:00:00 2001 From: TarikHamedovic Date: Tue, 23 Jul 2024 18:19:07 +0200 Subject: [PATCH 1/5] Added gatemate_a1_evb board --- amaranth_boards/gatemate_a1_evb.py | 305 +++++++++++++++++++++++++++++ 1 file changed, 305 insertions(+) create mode 100644 amaranth_boards/gatemate_a1_evb.py diff --git a/amaranth_boards/gatemate_a1_evb.py b/amaranth_boards/gatemate_a1_evb.py new file mode 100644 index 00000000..bc3458f4 --- /dev/null +++ b/amaranth_boards/gatemate_a1_evb.py @@ -0,0 +1,305 @@ +import os +import argparse +import subprocess +import shutil +import unittest + +from amaranth.build import * +from amaranth.vendor import GateMatePlatform +from .resources import * + + +__all__ = [ + "GateMate_A1_EVB" +] + +class _GateMate_A1_EVB(GateMatePlatform): + device = "GateMate_A1_EVB" + package = "CCGM1A1" + default_clk = "clk0" + + resources = [ + Resource("clk0", 0, Pins("IO_SB_A8", dir = "i"), Clock(10e6), Attrs(SCHMITT_TRIGGER="true")), + Resource("clk1", 0, Pins("IO_SB_A7", dir = "i"), Clock(10e6)), # GPIO23 + Resource("clk2", 0, Pins("IO_SB_A6", dir = "i"), Clock(10e6)), # GPIO24 + Resource("clk3", 0, Pins("IO_SB_A5", dir = "i"), Clock(10e6)), + + *LEDResources(pins = "IO_SB_B6", attrs=Attrs()), + *ButtonResources("fpga_but", pins="IO_SB_B7", attrs=Attrs()), + + + # Note: The documentation flipped the rx and tx pins + UARTResource(0, + rx="IO_SA_A6", tx="IO_SA_B6", role="dce" , attrs=Attrs() + ), + + # TODO: Check what is copi and cipo? + # TODO: Check where to place SPI_D0, SPI_D1, SPI_D2, SPI_D3 and FPGA_SPI_FWD? + #SPIResource(0, + # cs_n="IO_WA_A8", clk="IO_WA_B8" + #), + + PS2Resource(0, + clk="IO_WB_A0", dat="IO_WB_B0" + ), + + Resource("psram", 0, + Subsignal("psram_cs", Pins("IO_WC_A4", dir="o")), + Subsignal("psram_sclk", Pins("IO_WC_B4", dir="o")), + Subsignal("psram_data", Pins("IO_WC_A5 IO_WC_B5 IO_WC_A6 IO_WC_B6 " + "IO_WC_A7 IO_WC_B7 IO_WC_A8 IO_WC_B8", + dir="io")) + ), + + Resource("vga", 0, + Subsignal("hsync", Pins("IO_WB_A1", dir="o")), + Subsignal("vsync", Pins("IO_WB_B1", dir="o")), + Subsignal("red", Pins( + "IO_WB_B3" # Red_0 + "IO_WB_A3" # Red_1 + "IO_WB_B2" # Red_2 + "IO_WB_A2", # Red_3 + dir="o" + )), + Subsignal("green", Pins( + "IO_WB_B5" # Green_0 + "IO_WB_A5" # Green_1 + "IO_WB_B4" # Green_2 + "IO_WB_A4", # Green_3 + dir="o" + )), + Subsignal("blue", Pins( + "IO_WB_B7" # Blue_0 + "IO_WB_A7" # Blue_1 + "IO_WB_B6" # Blue_2 + "IO_WB_A6", # Blue_3 + dir="o" + )) + ), + + Resource("jtag", 0, + Subsignal("led", Pins("IO_SB_B5", dir="o")), + Subsignal("tck", Pins("IO_WA_A5", dir="i")), + Subsignal("tms", Pins("IO_WA_B4", dir="i")), + Subsignal("tdi", Pins("IO_WA_A4", dir="i")), + Subsignal("tdo", Pins("IO_WA_B3", dir="o")) + ), + + # TODO: Mybe the d Resource needs to be different input/output + Resource("spi", 0, + Subsignal("clk", Pins("IO_WA_B8", dir="o")), + Subsignal("csn", Pins("IO_WA_A8", dir="o")), + Subsignal("d", Pins("IO_WA_B7 IO_WA_A7 IO_WA_B6 IO_WA_A6" , dir="io")), + Subsignal("fwd", Pins("IO_WA_B5", dir="o")), + ), + + # TODO: Check how to declare LVDS pins + # TODO: Check direction of serdes pins + Resource("serdes", 0, + Subsignal("ser_clk_n", Pins("IO_SER_CLK_N", dir="io")), + Subsignal("ser_clk_p", Pins("IO_SER_CLK_P", dir="io")), + Subsignal("ser_tx_p", Pins("IO_SER_TX_P", dir="io")), + Subsignal("ser_tx_n", Pins("IO_SER_TX_N", dir="io")), + Subsignal("ser_rx_n", Pins("IO_SER_RX_N", dir="io")), + Subsignal("ser_rx_p", Pins("IO_SER_RX_P", dir="io")) + ), + + Resource("uext", 0, + Subsignal("txd", Pins("IO_EA_A0", dir ="o" )), + Subsignal("rxd", Pins("IO_EA_B0", dir ="i" )), + Subsignal("scl", Pins("IO_EA_A1", dir ="io")), + Subsignal("sda", Pins("IO_EA_B1", dir ="io")), + Subsignal("miso", Pins("IO_EA_A2", dir ="i" )), + Subsignal("mosi", Pins("IO_EA_B2", dir ="o" )), + Subsignal("sck", Pins("IO_EA_A3", dir ="o" )), + Subsignal("cs", Pins("IO_EA_B3", dir ="o" )), + ), + + Resource("pmod", 0, + Subsignal("1", Pins("IO_EA_A4", dir ="io")), + Subsignal("7", Pins("IO_EA_B4", dir ="io")), + Subsignal("2", Pins("IO_EA_A5", dir ="io")), + Subsignal("8", Pins("IO_EA_B5", dir ="io")), + Subsignal("3", Pins("IO_EA_A6", dir ="io")), + Subsignal("9", Pins("IO_EA_B6", dir ="io")), + Subsignal("4", Pins("IO_EA_A7", dir ="io")), + Subsignal("10", Pins("IO_EA_B7", dir ="io")), + ), + + + # Mostly used for RP2040 + Resource("gpio", 0, + Subsignal("0", Pins("IO_SA_A0", dir ="io")), + Subsignal("1", Pins("IO_SA_B0", dir ="io")), + Subsignal("2", Pins("IO_SA_A1", dir ="io")), + Subsignal("3", Pins("IO_SA_B1", dir ="io")), + Subsignal("4", Pins("IO_SA_A2", dir ="io")), + Subsignal("5", Pins("IO_SA_B2", dir ="io")), + Subsignal("6", Pins("IO_SA_A3", dir ="io")), + Subsignal("7", Pins("IO_SA_B3", dir ="io")), + Subsignal("8", Pins("IO_SA_A4", dir ="io")), + Subsignal("9", Pins("IO_SA_B4", dir ="io")), + Subsignal("10", Pins("IO_SA_A5", dir ="io")), + Subsignal("11", Pins("IO_SA_B5", dir ="io")), + Subsignal("14", Pins("IO_SA_A7", dir ="io")), + Subsignal("15", Pins("IO_SA_B7", dir ="io")), + Subsignal("21", Pins("IO_SB_B8", dir ="io")), # GPIN1 + Subsignal("26", Pins("IO_SB_B4", dir ="io")), + Subsignal("27", Pins("IO_SB_A4", dir ="io")), + Subsignal("28", Pins("IO_SB_A8", dir ="io")), + Subsignal("29", Pins("IO_SB_B8", dir ="io")), + ), + ] + + + connectors = [ + Connector("bank_na1", 0, { + # Lower Row (BOTTOM LEFT PIN IS VDD) + #"1" : "VDD" + "3": "IO_NA_A0", + "5": "IO_NA_A1", + "7": "IO_NA_A2", + "9": "IO_NA_A3", + "11": "IO_NA_A4", + "13": "IO_NA_A5", + "15": "IO_NA_A6", + "17": "IO_NA_A7", + "19": "IO_NA_A8", + # Upper Row (TOP LEFT PIN IS GND) + #"2" : "GND" + "4": "IO_NA_B0", + "6": "IO_NA_B1", + "8": "IO_NA_B2", + "10": "IO_NA_B3", + "12": "IO_NA_B4", + "14": "IO_NA_B5", + "16": "IO_NA_B6", + "18": "IO_NA_B7", + "20": "IO_NA_B8", + }), + + Connector("bank_nb1", 0, { + # Lower Row (BOTTOM LEFT PIN IS VDD) + #"1" : "VDD" + "3": "IO_NB_A0", + "5": "IO_NB_A1", + "7": "IO_NB_A2", + "9": "IO_NB_A3", + "11": "IO_NB_A4", + "13": "IO_NB_A5", + "15": "IO_NB_A6", + "17": "IO_NB_A7", + "19": "IO_NB_A8", + # Upper Row (TOP LEFT PIN IS GND) + #"2" : "GND" + "4": "IO_NB_B0", + "6": "IO_NB_B1", + "8": "IO_NB_B2", + "10": "IO_NB_B3", + "12": "IO_NB_B4", + "14": "IO_NB_B5", + "16": "IO_NB_B6", + "18": "IO_NB_B7", + "20": "IO_NB_B8", + }), + + Connector("bank_eb1", 0, { + # Lower Row (BOTTOM LEFT PIN IS VDD) + #"1" : "VDD" + "3": "IO_EB_A0", + "5": "IO_EB_A1", + "7": "IO_EB_A2", + "9": "IO_EB_A3", + "11": "IO_EB_A4", + "13": "IO_EB_A5", + "15": "IO_EB_A6", + "17": "IO_EB_A7", + "19": "IO_EB_A8", + # Upper Row (TOP LEFT PIN IS GND) + #"2" : "GND" + "4": "IO_EB_B0", + "6": "IO_EB_B1", + "8": "IO_EB_B2", + "10": "IO_EB_B3", + "12": "IO_EB_B4", + "14": "IO_EB_B5", + "16": "IO_EB_B6", + "18": "IO_EB_B7", + "20": "IO_EB_B8", + }), + + Connector("bank_misc1", 0, { + # Left Row (TOP LEFT PIN IS 2.5V) + #"1" : "2.5V" + "fpga_spi_fwd": "IO_WA_B5", # 3 + "5": "IO_EA_A8", + "7": "IO_EA_B8", + "9": "IO_WB_A8", + "11": "IO_WB_B8", + "13": "IO_SB_B3", + "15": "IO_SB_A3", + "17": "IO_SB_B2", + "19": "IO_SB_A2", + "21": "IO_SB_B1", + "23": "IO_SB_A1", + "25": "IO_SB_B0", + "27": "IO_SB_A0", + "fpga_reset_in": "RST_N", + # Right Row (TOP RIGHT PIN IS 1.8V) + #"2" : "1.8V" + "4": "IO_WC_B3", + "6": "IO_WC_A3", + "8": "IO_WC_B2", + "10": "IO_WC_A2", + "12": "IO_WC_B1", + "14": "IO_WC_A1", + "16": "IO_WC_B0", + "18": "IO_WC_A0", + # SerDes + "18": "IO_SER_CLK_N", + "20": "IO_SER_CLK_P", + "22": "IO_SER_TX_P", + "24": "IO_SER_TX_N", + "26": "IO_SER_RX_N", + "28": "IO_SER_RX_P" + }) + ] + + @property + def required_tools(self): + return super().required_tools + [ + "openFPGALoader" + ] + + def toolchain_prepare(self, fragment, name, **kwargs): + overrides = dict(yosys_opts="-p 'synth_gatemate -top {} -nomx8 -vlog'".format(name), + pr_opts="-v -ccP", + openfpgaloader_opts="-b gatemate_evb_jtag --cable dirtyJtag") + overrides.update(kwargs) + return super().toolchain_prepare(fragment, name, **overrides) + + + def toolchain_program(self, products, name): + tool = os.environ.get("OPENFPGALOADER", "openFPGALoader") + with products.extract("{}_00.cfg.bit".format(name)) as bitstream_filename: + subprocess.check_call([tool, "-b", "gatemate_evb_jtag", "--cable", "dirtyJtag", bitstream_filename]) + +class GateMate_A1_EVB(_GateMate_A1_EVB): + name = "Olimex GateMateA1-EVB" + +class TestCase(unittest.TestCase): + def test_smoke(self): + from .test.blinky import Blinky + GateMate_A1_EVB().build(Blinky(), do_build= False) + + + +if __name__ == "__main__": + from .test.blinky import * + + variants = [] # No variants so far + + platform = GateMate_A1_EVB() + platform.build(Blinky(), do_program=True) + + From 0fa51c4efeffb1a1c72079dac4efcd5872b9bcb9 Mon Sep 17 00:00:00 2001 From: TarikHamedovic Date: Wed, 24 Jul 2024 02:03:57 +0200 Subject: [PATCH 2/5] Pull Request Update --- amaranth_boards/gatemate_a1_evb.py | 106 ++++++++++------------------- 1 file changed, 36 insertions(+), 70 deletions(-) diff --git a/amaranth_boards/gatemate_a1_evb.py b/amaranth_boards/gatemate_a1_evb.py index bc3458f4..3c698f5d 100644 --- a/amaranth_boards/gatemate_a1_evb.py +++ b/amaranth_boards/gatemate_a1_evb.py @@ -13,7 +13,7 @@ "GateMate_A1_EVB" ] -class _GateMate_A1_EVB(GateMatePlatform): +class GateMate_A1_EVB(GateMatePlatform): device = "GateMate_A1_EVB" package = "CCGM1A1" default_clk = "clk0" @@ -44,37 +44,19 @@ class _GateMate_A1_EVB(GateMatePlatform): ), Resource("psram", 0, - Subsignal("psram_cs", Pins("IO_WC_A4", dir="o")), - Subsignal("psram_sclk", Pins("IO_WC_B4", dir="o")), - Subsignal("psram_data", Pins("IO_WC_A5 IO_WC_B5 IO_WC_A6 IO_WC_B6 " + Subsignal("cs", Pins("IO_WC_A4", dir="o")), + Subsignal("sclk", Pins("IO_WC_B4", dir="o")), + Subsignal("data", Pins("IO_WC_A5 IO_WC_B5 IO_WC_A6 IO_WC_B6 " "IO_WC_A7 IO_WC_B7 IO_WC_A8 IO_WC_B8", dir="io")) ), - - Resource("vga", 0, - Subsignal("hsync", Pins("IO_WB_A1", dir="o")), - Subsignal("vsync", Pins("IO_WB_B1", dir="o")), - Subsignal("red", Pins( - "IO_WB_B3" # Red_0 - "IO_WB_A3" # Red_1 - "IO_WB_B2" # Red_2 - "IO_WB_A2", # Red_3 - dir="o" - )), - Subsignal("green", Pins( - "IO_WB_B5" # Green_0 - "IO_WB_A5" # Green_1 - "IO_WB_B4" # Green_2 - "IO_WB_A4", # Green_3 - dir="o" - )), - Subsignal("blue", Pins( - "IO_WB_B7" # Blue_0 - "IO_WB_A7" # Blue_1 - "IO_WB_B6" # Blue_2 - "IO_WB_A6", # Blue_3 - dir="o" - )) + + VGAResource("vga", 0, + r="IO_WB_B3 IO_WB_A3 IO_WB_B2 IO_WB_A2", + g="IO_WB_B5 IO_WB_A5 IO_WB_B4 IO_WB_A4", + b="IO_WB_B7 IO_WB_A7 IO_WB_B6 IO_WB_A6", + vs= "IO_WB_B1", + hs="IO_WB_A1" ), Resource("jtag", 0, @@ -85,7 +67,6 @@ class _GateMate_A1_EVB(GateMatePlatform): Subsignal("tdo", Pins("IO_WA_B3", dir="o")) ), - # TODO: Mybe the d Resource needs to be different input/output Resource("spi", 0, Subsignal("clk", Pins("IO_WA_B8", dir="o")), Subsignal("csn", Pins("IO_WA_A8", dir="o")), @@ -93,39 +74,11 @@ class _GateMate_A1_EVB(GateMatePlatform): Subsignal("fwd", Pins("IO_WA_B5", dir="o")), ), - # TODO: Check how to declare LVDS pins - # TODO: Check direction of serdes pins Resource("serdes", 0, - Subsignal("ser_clk_n", Pins("IO_SER_CLK_N", dir="io")), - Subsignal("ser_clk_p", Pins("IO_SER_CLK_P", dir="io")), - Subsignal("ser_tx_p", Pins("IO_SER_TX_P", dir="io")), - Subsignal("ser_tx_n", Pins("IO_SER_TX_N", dir="io")), - Subsignal("ser_rx_n", Pins("IO_SER_RX_N", dir="io")), - Subsignal("ser_rx_p", Pins("IO_SER_RX_P", dir="io")) - ), - - Resource("uext", 0, - Subsignal("txd", Pins("IO_EA_A0", dir ="o" )), - Subsignal("rxd", Pins("IO_EA_B0", dir ="i" )), - Subsignal("scl", Pins("IO_EA_A1", dir ="io")), - Subsignal("sda", Pins("IO_EA_B1", dir ="io")), - Subsignal("miso", Pins("IO_EA_A2", dir ="i" )), - Subsignal("mosi", Pins("IO_EA_B2", dir ="o" )), - Subsignal("sck", Pins("IO_EA_A3", dir ="o" )), - Subsignal("cs", Pins("IO_EA_B3", dir ="o" )), - ), - - Resource("pmod", 0, - Subsignal("1", Pins("IO_EA_A4", dir ="io")), - Subsignal("7", Pins("IO_EA_B4", dir ="io")), - Subsignal("2", Pins("IO_EA_A5", dir ="io")), - Subsignal("8", Pins("IO_EA_B5", dir ="io")), - Subsignal("3", Pins("IO_EA_A6", dir ="io")), - Subsignal("9", Pins("IO_EA_B6", dir ="io")), - Subsignal("4", Pins("IO_EA_A7", dir ="io")), - Subsignal("10", Pins("IO_EA_B7", dir ="io")), + Subsignal("clk", DiffPairs("IO_SER_CLK_N IO_SER_CLK_P", "complement")), + Subsignal("tx", DiffPairs("IO_SER_TX_P IO_SER_TX_N", "complement")), + Subsignal("rx", DiffPairs("IO_SER_RX_N IO_SER_RX_P", "complement")), ), - # Mostly used for RP2040 Resource("gpio", 0, @@ -262,14 +215,31 @@ class _GateMate_A1_EVB(GateMatePlatform): "24": "IO_SER_TX_N", "26": "IO_SER_RX_N", "28": "IO_SER_RX_P" + }), + + Connector("pmod", 0, { + 1: "IO_EA_A4", + 7: "IO_EA_B4", + 2: "IO_EA_A5", + 8: "IO_EA_B5", + 3: "IO_EA_A6", + 9: "IO_EA_B6", + 4: "IO_EA_A7", + 10: "IO_EA_B7" + }), + + Connector("uext", 0, { + "txd": "IO_EA_A0", + "rxd": "IO_EA_B0", + "scl": "IO_EA_A1", + "sda": "IO_EA_B1", + "miso": "IO_EA_A2", + "mosi": "IO_EA_B2", + "sck": "IO_EA_A3", + "cs": "IO_EA_B3" }) ] - @property - def required_tools(self): - return super().required_tools + [ - "openFPGALoader" - ] def toolchain_prepare(self, fragment, name, **kwargs): overrides = dict(yosys_opts="-p 'synth_gatemate -top {} -nomx8 -vlog'".format(name), @@ -284,8 +254,6 @@ def toolchain_program(self, products, name): with products.extract("{}_00.cfg.bit".format(name)) as bitstream_filename: subprocess.check_call([tool, "-b", "gatemate_evb_jtag", "--cable", "dirtyJtag", bitstream_filename]) -class GateMate_A1_EVB(_GateMate_A1_EVB): - name = "Olimex GateMateA1-EVB" class TestCase(unittest.TestCase): def test_smoke(self): @@ -297,8 +265,6 @@ def test_smoke(self): if __name__ == "__main__": from .test.blinky import * - variants = [] # No variants so far - platform = GateMate_A1_EVB() platform.build(Blinky(), do_program=True) From 102725434d80e4453bf891d56d2d17e5a3331857 Mon Sep 17 00:00:00 2001 From: TarikHamedovic Date: Thu, 25 Jul 2024 00:38:43 +0200 Subject: [PATCH 3/5] Update --- amaranth_boards/gatemate_a1_evb.py | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/amaranth_boards/gatemate_a1_evb.py b/amaranth_boards/gatemate_a1_evb.py index 3c698f5d..d92d7bfa 100644 --- a/amaranth_boards/gatemate_a1_evb.py +++ b/amaranth_boards/gatemate_a1_evb.py @@ -75,9 +75,9 @@ class GateMate_A1_EVB(GateMatePlatform): ), Resource("serdes", 0, - Subsignal("clk", DiffPairs("IO_SER_CLK_N IO_SER_CLK_P", "complement")), - Subsignal("tx", DiffPairs("IO_SER_TX_P IO_SER_TX_N", "complement")), - Subsignal("rx", DiffPairs("IO_SER_RX_N IO_SER_RX_P", "complement")), + Subsignal("clk", DiffPairs("IO_SER_CLK_N", "IO_SER_CLK_P")), + Subsignal("tx", DiffPairs("IO_SER_TX_P", "IO_SER_TX_N")), + Subsignal("rx", DiffPairs("IO_SER_RX_N", "IO_SER_RX_P")), ), # Mostly used for RP2040 @@ -218,14 +218,14 @@ class GateMate_A1_EVB(GateMatePlatform): }), Connector("pmod", 0, { - 1: "IO_EA_A4", - 7: "IO_EA_B4", - 2: "IO_EA_A5", - 8: "IO_EA_B5", - 3: "IO_EA_A6", - 9: "IO_EA_B6", - 4: "IO_EA_A7", - 10: "IO_EA_B7" + "1": "IO_EA_A4", + "7": "IO_EA_B4", + "2": "IO_EA_A5", + "8": "IO_EA_B5", + "3": "IO_EA_A6", + "9": "IO_EA_B6", + "4": "IO_EA_A7", + "10": "IO_EA_B7" }), Connector("uext", 0, { From 6c3877f8fa309eec5c2048471452da8ee4d38f2d Mon Sep 17 00:00:00 2001 From: TarikHamedovic Date: Thu, 8 Aug 2024 19:51:13 +0200 Subject: [PATCH 4/5] Added GateMate Eval Board blink and led --- amaranth_boards/gatemate_a1_evb.py | 9 ----- amaranth_boards/gatemate_eval_board.py | 52 ++++++++++++++++++++++++++ 2 files changed, 52 insertions(+), 9 deletions(-) create mode 100644 amaranth_boards/gatemate_eval_board.py diff --git a/amaranth_boards/gatemate_a1_evb.py b/amaranth_boards/gatemate_a1_evb.py index d92d7bfa..0015ba67 100644 --- a/amaranth_boards/gatemate_a1_evb.py +++ b/amaranth_boards/gatemate_a1_evb.py @@ -240,15 +240,6 @@ class GateMate_A1_EVB(GateMatePlatform): }) ] - - def toolchain_prepare(self, fragment, name, **kwargs): - overrides = dict(yosys_opts="-p 'synth_gatemate -top {} -nomx8 -vlog'".format(name), - pr_opts="-v -ccP", - openfpgaloader_opts="-b gatemate_evb_jtag --cable dirtyJtag") - overrides.update(kwargs) - return super().toolchain_prepare(fragment, name, **overrides) - - def toolchain_program(self, products, name): tool = os.environ.get("OPENFPGALOADER", "openFPGALoader") with products.extract("{}_00.cfg.bit".format(name)) as bitstream_filename: diff --git a/amaranth_boards/gatemate_eval_board.py b/amaranth_boards/gatemate_eval_board.py new file mode 100644 index 00000000..99d0bad9 --- /dev/null +++ b/amaranth_boards/gatemate_eval_board.py @@ -0,0 +1,52 @@ +import os +import argparse +import subprocess +import shutil +import unittest + +from amaranth.build import * +from amaranth.vendor import GateMatePlatform +from .resources import * + + +__all__ = [ + "GateMate_Eval_Board" +] + +class GateMate_Eval_Board(GateMatePlatform): + device = "GateMate_Eval_Board" + package = "CCGM1A1" + default_clk = "clk0" + + resources = [ + Resource("clk0", 0, Pins("IO_SB_A8", dir = "i"), Clock(10e6), Attrs(SCHMITT_TRIGGER="true")), + + *LEDResources(pins = "IO_EB_B1", attrs=Attrs()), + *ButtonResources("but", pins="IO_EB_B0", attrs=Attrs()), + + ] + + connectors = [] + + + def toolchain_program(self, products, name): + tool = os.environ.get("OPENFPGALOADER", "openFPGALoader") + with products.extract("{}_00.cfg.bit".format(name)) as bitstream_filename: + subprocess.check_call([tool, "-b", "gatemate_evb_jtag", "--cable", "dirtyJtag", bitstream_filename]) + + +class TestCase(unittest.TestCase): + def test_smoke(self): + from .test.blinky import Blinky + GateMate_Eval_Board().build(Blinky(), do_build= False) + + + +if __name__ == "__main__": + from .test.blinky import * + + platform = GateMate_Eval_Board() + platform.build(Blinky(), do_program=True) + + + From 63d018b9a9c41d65199d2fe2661a43822f5f9d78 Mon Sep 17 00:00:00 2001 From: TarikHamedovic Date: Thu, 8 Aug 2024 22:02:19 +0200 Subject: [PATCH 5/5] Update --- amaranth_boards/gatemate_a1_evb.py | 1 - 1 file changed, 1 deletion(-) diff --git a/amaranth_boards/gatemate_a1_evb.py b/amaranth_boards/gatemate_a1_evb.py index 0015ba67..80f6fa55 100644 --- a/amaranth_boards/gatemate_a1_evb.py +++ b/amaranth_boards/gatemate_a1_evb.py @@ -8,7 +8,6 @@ from amaranth.vendor import GateMatePlatform from .resources import * - __all__ = [ "GateMate_A1_EVB" ]