Remove vc707

docs/library/jesd204/index.rst

@@ -423,7 +423,6 @@ HDL Example Projects
   - :git-hdl:`Intel A10Gx (RETIRED) <hdl_2021_r1:projects/daq2/a10gx>`
   - :git-hdl:`AMD Xilinx KC705 <projects/daq2/kc705>`
   - :git-hdl:`AMD Xilinx KCU105 <projects/daq2/kcu105>`
-  - :git-hdl:`AMD Xilinx VC707 (RETIRED) <hdl_2018_r2:projects/daq2/vc707>`
   - :git-hdl:`AMD Xilinx ZC706 <projects/daq2/zc706>`
   - :git-hdl:`AMD Xilinx ZCU102 <projects/daq2/zcu102>`
 
@@ -495,7 +494,6 @@ HDL Example Projects
 
 - :ref:`AD6676EVB Reference Design <ad6676evb>` on:
 
-  - :git-hdl:`AMD Xilinx VC707 <projects/ad6676evb/vc707>`
   - :git-hdl:`AMD Xilinx ZC706 <projects/ad6676evb/zc706>`
 
 - :ref:`AD9083-EVB Reference Design <ad9083_evb>` on:

docs/projects/ad6676evb/index.rst

@@ -41,12 +41,18 @@ Supported carriers
      - Carrier
      - FMC slot
    * - :adi:`EVAL-AD6676`
-     - :xilinx:`VC707`
+     - :xilinx:`VC707` *
      - FMC1 HPC
    * -
      - :xilinx:`ZC706`
      - FMC HPC
 
+.. admonition:: Legend
+   :class: note
+
+   - ``*`` removed; last release that supports this project on this carrier is
+      :git-hdl:`hdl_2023_r2 <hdl_2023_r2:projects/ad6676_evb/vc707>`
+
 Block design
 -------------------------------------------------------------------------------
 
@@ -247,27 +253,17 @@ the HDL repository.
 
 **Linux/Cygwin/WSL**
 
-Building the VC707/ZC706 project with the default configuration,
+Building the ZC706 project with the default configuration,
 RX_JESD_L=2 lanes.
 
-.. shell:: bash
-
-   $cd hdl/projects/ad6676evb/vc707
-   $make
-
 .. shell:: bash
 
    $cd hdl/projects/ad6676evb/zc706
    $make
 
-Building the VC707/ZC706 project with the other available configuration,
+Building the ZC706 project with the other available configuration,
 with just **one lane**:
 
-.. shell:: bash
-
-   $cd hdl/projects/ad6676evb/vc707
-   $make RX_JESD_L=1
-
 .. shell:: bash
 
    $cd hdl/projects/ad6676evb/zc706

docs/projects/fmcomms2/index.rst

@@ -62,7 +62,7 @@ Supported carriers
      - :xilinx:`KCU105`
      - FMC LPC
    * -
-     - :xilinx:`VC707`
+     - :xilinx:`VC707` *
      - FMC HPC1
    * -
      - :xilinx:`ZC702`
@@ -77,6 +77,12 @@ Supported carriers
      - `ZedBoard <https://digilent.com/shop/zedboard-zynq-7000-arm-fpga-soc-development-board>`__
      - FMC LPC
 
+.. admonition:: Legend
+   :class: note
+
+   - ``*`` removed; last release that supports this project on this carrier is
+      :git-hdl:`hdl_2023_r2 <hdl_2023_r2:projects/fmcomms2/vc707>`
+
 Block design
 -------------------------------------------------------------------------------