asic-verification

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be …

asic fpga vhdl rtl verilog synthesis fft soc asic-verification asic-design

Updated Dec 3, 2023
Verilog

Lampro-Mellon / Quasar

Star

Quasar 2.0: Chisel equivalent of SweRV-EL2

scala processor chisel riscv rtl chisel3 open-source-hardware verilator asic-verification axi4 ahb-lite asic-design swerv swerv-el2

Updated Apr 13, 2021
Scala

m-kru / go-hdl

Star

Hdl is a tool for easing the work with hardware description languages.

asic fpga vhdl asic-verification

Updated Dec 12, 2022
Go

abdelazeem201 / LEON2

Star

The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.

arm asic fpga simulation vhdl rtl verilog systemverilog soc asic-verification asic-design

Updated May 6, 2023
VHDL

SalomeDevkule7 / Neural-Network-Layer-Generator

Star

Application Specific Integrated Circuit(ASIC)

neural-networks vlsi systemverilog-hdl asic-verification

Updated Jun 7, 2018
SystemVerilog

williaml33moore / bathtub

Star

BDD Gherkin implementation in native SystemVerilog, based on UVM.

asic fpga bdd bdd-specs rtl verilog systemverilog uvm verilog-hdl bdd-framework asic-verification design-verification asic-design rtl-design soc-design soc-verification uvm-verification

Updated Nov 16, 2024
SystemVerilog

kumarrishav14 / I2C

Star

VIP for I2C

i2c uvm system-verilog asic-verification design-verification

Updated Jun 7, 2022

Aperture-Electronic / Indago.NET

Star

.NET Scripting Engine for Cadence(R) Indago(R) Interactive Verification Enviroment

fpga csharp dotnet vhdl verilog cadence asic-verification indago

Updated Jan 26, 2024
C#

dhruvildarji / MIPS

Star

Made Million Instruction Per Second Processor

mips vhdl microprocessor vlsi asic-verification

Updated Feb 24, 2018

jpm18 / VLSI-Laboratory-NIT-Rourkela

Star

Laboraory manuals and Discussion

asic asic-verification

Updated Oct 19, 2023
Verilog

rehanmq / asic-soc-ml-accelerator-verification

Star

End-to-end ASIC SoC design and functional verification of a lightweight machine learning accelerator using SystemVerilog and UVM. Includes Python automation for test generation and result analysis. Built to simulate real-world ML silicon validation at scale.

systemverilog msp432 system-design verilator asic-verification soc-design ai-hardware

Updated Mar 26, 2025
Verilog

pkpkp456 / Learn_System_Verilog

Star

Dive into the world of SystemVerilog with hands-on projects that bring RTL design and verification to life! From blinking counters to smart assertions, this repo is my personal sandbox for mastering the language behind modern chip design. Whether you're a VLSI enthusiast, an aspiring verification engineer, or just curious about how hardware think.

verilog systemverilog digital-design asic-verification hardware-verification fpga-projects rtl-design-and-verification